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Etude de la fiabilité des composants soumis à des stress éléctriques conduits

Feiyi Zhu 1
1 Pôle Electronique et Systèmes
IRSEEM - Institut de Recherche en Systèmes Electroniques Embarqués
Abstract : Accurate method of reliability qualification is required to meet the needs of the electronic embedded components and systems. It was found that the undesirable effects as OVS (Over-current and over-voltage) part of EOS (Electrical Overstress) can be the cause of electronic component and system failure. Moreover, these effects are not yet classified in the standard test procedures. As a corollary, relevant test method and model need to be developed in order to improve the electronic component reliability against the OVS and EOS effects. The main objective of the present PhD thesis which was conducted in IRSEEM and involved in the SESAMES project (Study for Electrical overstress Standardization And Measuring Equipment Set-up) is to develop a test bench for the characterization of the electronic components against the EOS effects. The conducted research work is to improve the knowledge of the electronic design and manufacturing engineers about the EOS influence on the component reliability. A study subjected to the characterization of electronic components for different family of the EOS was conducted. To understand the mechanism of electronic components degradation during and after pulsed EOS, a test bench was developed. The EOS test platform operation was described including the implementation of the pulsed EOS signals generation approach based on the Matlab and LabVIEW programming. For different EOS waveforms, after description of the experimental test set-up, the EOS test results were presented and discussed. To meet the needs of SESAME project industrial partners, two different electronic components ware tested and studied. It acts as a Zener diode and the TDA8007 CMOS integrated circuits. After the failure analyses of the tested components, the electrical mechanism illustrating the reasons of the component degradation due to the EOSs were interpreted and commented. Based on the investigation on the EOS tested components from SEM (Scanning Electron Microscopy) and FIB (Focused Ion Beam), illustration on the electrical mechanism of the tested component degradation were presented and interpreted. This failure analysis enables to locate and understand the degradation sources and the electrical state of the tested components reliability. To predict the tested component reliability during and after EOS, an electrical model was developed. The typically thermo-electrical model was implemented in VHDL-AMS (VHSIC Hardware Description Language - Analog and Mixed Systems) language and implemented into the simulation tool based on the SPICE environment. A methodology enabling the identification of the tested diode electrical model during and after EOS was established. Then, the developed model was validated by SPICE (Simulation Program with Integrated Circuit Emphasis) simulations and experimental results. The developed model could be used in the future to predict the failure of the electronic systems against to the EOS effects.
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  • HAL Id : tel-02889289, version 1

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Feiyi Zhu. Etude de la fiabilité des composants soumis à des stress éléctriques conduits. Electronique. Université de Rouen Normandie, 2015. Français. ⟨tel-02889289⟩

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